06:01
Tom
Your phone/tablet is about to be outdated. But so goes the Android life, I suppose. It moves fast. A speed pushed forward by not only smartphone manufacturers, but chipset OEM?s as well.
Today, ARM has announced the next generation of their Cortext series chips with the first implementation of the A15 in a quad-core hard macro layout. You may remember a few benchmarks a while back where Qualcomm?s dual-core S4 chipset (comparable to the A15 architecture) went up against the quad-core Nvidia Tegra 3 processor (based on the older A9 architecture) and in many cases, that little dual-core, based on a 28-nanometer process, bested the quad. Now, just imagine those benchmarks when you throw in a quad-core A15 into the mix and (shudder), I just got goosebumps.
Apparently, ARM has designed the new quad-core A15 for manufacturers to easily add to their chips with little fuss. No word on who will jump on this new tech (or even if we really need something so powerful in our tablets/phones) but here?s to hoping we see something soon. Full press release below.
17 April 2012
Power-optimized implementation of quad-core hard macro on leading 28nm process
CAMBRIDGE, UK - April 17, 2012- ARM today announced the availability of a high performance, power-optimized quad-core hard macro implementation of its flagship ARM� Cortex?-A15 MPCore? processor.
The ARM�Cortex-A15 MP4 hard macro is designed to run at 2GHz and delivers performance in excess of 20,000DMIPS, while maintaining the power efficiency of the Cortex-A9 hard macro. The Cortex-A15 hard macro development is the result of the unique synergy arising from the combination of ARM Cortex processor IP, Artisan� physical IP, CoreLink? systems IP and ARM integration capabilities, and utilizes the TSMC 28HPM process.
The low leakage implementation, featuring integrated NEON? SIMD technology and floating point (VFP), delivers an extremely competitive balance of performance and power and is ideal for wide array of high-performance computing applications for such as notebooks through to power-efficient, extreme performance-orientated network and enterprise devices.
The hard macro was developed using ARM Artisan 12-track libraries and the recently announced Processor Optimization Pack? (POP) solution for the Cortex-A15 on TSMC 28nm HPM process. This follows the recent announcement of a broad suite of POPs for all Cortex-A series processors (see ARM Expands Processor Optimization Pack Solutions for TSMC 40nm and 28nm Process Variants, 16th April 2012)
Full configuration and implementation details will be presented at the Cool Chips conference (18-20 April) in Yokohama, Japan. Further information is contained in an accompanying blog.
"For SoC designers looking to make a trade-off between the flexibility offered by the traditional RTL-based SoC development strategy and a rapid time to market, with ensured, benchmarked power, performance and area, an ARM hard macro implementation is an ideal, cost-effective solution," said Jim Nicholas, vice president of Marketing, processor division, ARM. "This new Cortex-A15 hard macro is an important addition to our portfolio and will enable a wider array of partners to leverage the outstanding capabilities of the Cortex-A15 processor."
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